Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions, and personal computing devices, as examples. Such integrated circuits typically use multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. To provide the necessary signal and power interconnections for the multiplicity of semiconductor devices, many integrated circuits now include multiple levels of metallization.
The semiconductor industry continuously strives to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of the circuits necessary for today's advanced semiconductor products. The increasing density has lead to the need for more metallic layers, typically of aluminum and more recently of copper, to provide the circuit interconnections. For CMOS ICs with 250 nm feature size, four metallic layers for interconnections was sufficient. Below 100 nm, nine or more metallic layers will generally be required. With the increasing number of metallic interconnection layers, more manufacturing steps and cost are required to form the interconnections than the transistors and diodes in the semiconductor device. For high complexity, high density chips with six or more layers of metallization, the total length of the layered interconnect wiring in the chip can be of the order of a mile. The signaling speed among on-chip devices provided by these interconnections has become a significant factor in chip performance. The resistance of the interconnecting wiring generally increases as a consequence of its width-height product being reduced faster than its length is shortened, which further aggravates the signaling-speed problem.
A layered and patterned metal interconnect structure is conventionally formed in the upper layers of an integrated circuit to provide the necessary circuit connections for the various semiconductor devices in the integrated circuit such as transistors and diodes. In high-density integrated circuits, damascene techniques are used to form and deposit metal lines and vias for the desired interconnections in a surrounding dielectric layer.
In ordinary damascene processes, trenches and vias are patterned and dry-etched during BEOL processing (“back end of line” processing, which is the processing performed after the first metallic contacts are formed on the die), typically to a depth of about 0.2 to 0.5 μm, in a dielectric layer using lithographic techniques. A trench and/or a via is first lined with a thin liner material such as tantalum, and then entirely filled with a metal, preferably copper in advanced processes. Excess metal deposited outside the trench is removed by a CMP (chemical-mechanical polishing) process, leaving a clean metal line or via substantially planarized with the surrounding dielectric. The via- and trench-forming steps are repeated to produce a number of layers of interconnected metallic lines for the underlying semiconductor devices.
Advanced CMOS processes, particularly CMOS processes producing fine-line structures smaller than 100 nm, employ low-k and ultra-low-k dielectric materials for the intermetallic and intrametallic dielectric layers in order to reduce capacitive coupling between interconnect lines and thereby reduce signaling delays. The parameter “k” is the relative dielectric constant for the material, where a vacuum has a value of one for k. Using a dielectric material with low dielectric constant is thus important in semiconductor devices with reduced feature sizes. But low-k dielectric materials can be difficult to use, and without due care are generally not robust in manufacturing processes. For example, widely used low-k materials generally comprise organic spin-on materials, which must be heated after application to remove the liquid or solvent. Low-k materials generally have a high thermal expansion coefficient compared to metals and silicon dioxide, and have a lower moisture and chemical resistance. These materials with low dielectric constant are not easily etched or cleaned, and are typically damaged by dry-etching processes, causing them to at least partially lose their low-k properties. Porous dielectrics, often used for their low dielectric constant, are particularly prone to these effects, resulting in unreliable or low-performing products.
FIGS. 1 and 2 show prior art structures (layers of dies on wafers) 100 and 160 for prior methods of fabricating multi-layer interconnects of an integrated circuit on a semiconductor wafer. FIG. 1 shows a single-damascene approach, and FIG. 2 shows a dual-damascene approach.
Referring first to the structure 100 shown in FIG. 1, a substrate 102 is provided, typically comprising silicon dioxide deposited over single-crystal silicon. The substrate 102 may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors such as GaAs, InP, Si/Ge, SiC are often used in place of silicon.
A first dielectric layer 104 is deposited over the substrate 102. In the prior art structure described herein, dielectric 104 comprises a low-dielectric constant material, having a relative dielectric constant k of 3.6 or less, for example. Low-k dielectric material 104 comprises an organic spin-on material such as a polyimide or others. Trademarks for such materials include Dow Chemical Company's SiLK™ and AlliedSignal, Inc.'s Flare™ for example. After depositing a low-k dielectric 104 typically by CVD, the wafer 100 is exposed in a heating step (e.g., baked) to remove the solvents and cure the dielectric material. Temperatures of the heating step may reach 400° C., for example. Other low-k dielectrics can be deposited by chemical vapor deposition.
Dielectric material 104 is patterned and etched, generally using an RIE (reactive ion etch) or other etching process, and conductive lines 108 are formed. An optional conductive liner 106 (which is necessary as a barrier for Cu) may be deposited prior to formation of conductive lines 108. Conductive liner 106 typically comprises Ta, TaN, WN, TiN, etc., and conductive lines 108 may comprise conductive materials such as aluminum, copper, other metals, or combinations thereof, for example.
A dielectric cap layer 110 comprising Si3N4, for example, is deposited over conductive lines 108 and low-k dielectric 104. A second layer of dielectric material 112 is deposited over conductive lines 108. Second dielectric layer 112 comprises a low-k material and thus is often baked at up to 400° C. to remove solvents. Dielectric layer 112 is patterned, e.g., with a mask, and via openings are formed using an etch process step, preferably an anisotropic etch process which is substantially directed towards the perpendicular surface of the wafer. A small portion of the tops of conductive lines 108 is typically etched during the anisotropic etch process, as shown by the recess at 122.
A metallic liner 117 must be deposited over the a hole for a via and a trench for a metal line. The via openings are filled with a metallic material, preferably the same as the material used for the conductive lines 108, for example, copper, to form vias 116. Vias 116 are typically substantially cylindrical, and may have a slightly greater diameter at the tops than at the bottoms due to the via opening etch process not being entirely perpendicular to the wafer 100 surface.
A third dielectric layer 114 comprising a low-k dielectric material, for example, OMCTS (octamethylcyclotetrasiloxane), is deposited over vias 116, heated to remove the solvents, patterned, and etched. Conductive lines 120 are formed over vias 116 to provide a connection to conductive lines 108 in the underlying first dielectric layer 104. An optional conductive liner 118 may be deposited prior to the formation of conductive lines 120. Conductive lines 120 preferably comprise a metal material the same as conductive lines 108, for example. Many other conductive layers may be deposited in this manner. It is now not uncommon to have six or more conductive layers within a semiconductor structure as the complexity of devices continues to increase.
FIG. 2 shows generally at 160 a prior art dual-damascene approach of forming multi-layer interconnects of an integrated circuit. A substrate 102 is provided, and a first dielectric layer 104 is deposited over the substrate 102. Dielectric material 104 may comprise a low-k dielectric. Dielectric material 104 is patterned and etched, and conductive lines 108 are formed. An optional conductive liner 106 may be deposited prior to formation of conductive lines 108.
A dielectric cap layer 110 is deposited over conductive lines 108 and low-k dielectric 104. A second layer of dielectric material 162 is deposited over conductive lines 108. In a dual damascene approach, second dielectric layer 162 is thicker than in a single-damascene approach, because both via 170 and metal line 168 are formed within the second dielectric layer 162. Alternatively, an etch stop material 171 may be deposited near the interface of the via 170 and metal line 168, as shown in phantom.
Dielectric layer 162 is patterned and etched, generally in two separate steps to form via 170 holes and trenches for metal lines 168. The via 170 hole may be formed first, followed by the formation of metal line 168 trench, or vice versa. A metallic liner 164 must be deposited over the via hole and the metal line trench. The via openings and metal line trench are filled with a metallic material, preferably the same as the material used for the conductive lines 108, for example, to form vias 170 and metal lines 168.
Thus, in prior art processes, copper (or other metal) conductors to interconnect devices are formed in back-end-of-line (BEOL) processes using single- or dual-damascene techniques, and preferably use a dielectric with a low dielectric constant. Lithography followed by dry-etch steps create vias and trenches in the dielectric layer. In production processes, vias and trenches are often produced using via-first methods wherein a first lithographic process creates a via pattern to etch down to a metallic layer below a dielectric layer, and a second lithographic process creates a trench pattern co-aligned with the via. Via-first methods employ an OPL (organic planarizing layer) to fill the vias and to provide a level surface for the following trench lithography. After the trench is patterned, exposed, and etched, the organic planarizing material should be completely removed to prevent interference with following processes.
But a principal limitation of prior-art processes is the inability to form metallic interconnects with high-speed signal transmission characteristics and high reliability, particularly for devices with structures smaller than 100 nm and gate counts exceeding one million gates. State-of-the-art damascene patterning of the ILD (inter-layer dielectrics) using an RIE or other etching process induces ILD damage particularly adjacent to openings in the ILD patterns, resulting in an increased value for the dielectric constant in the surrounding dielectric region. Interconnect patterns with reduced dimensions generally result in an increased fraction of damaged dielectric material compared to non-damaged bulk dielectric material, and thus have an increased effective dielectric constant. A need thus exists for an improved process and method that can overcome these deficiencies by avoiding damage to the dielectric material during the dielectric patterning and etching processes for forming vias and trenches for metallic interconnects. The need is for a technology to produce metallic interconnects with low interline capacitance, preferably using low-k and ultra-low-k (porous) materials. The need for a damage-free approach is even more important for future generations of integrated circuits because higher density interconnect patterns with higher aspect ratios make it difficult to achieve thin and homogeneous liner coverage on via and trench sidewalls with state-of-the-art lithography.